Book
Vhdl Modeling For Digital Design Synthesis
VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. This text covers the synthesis aspects of VHDL, keeping the simulation specifics to a minimum. «
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Author(s):
Riverside, Usa) Liu Jessie T. (Dept. Of Computer Science, Eric S. Lin, Kevin F. Tsai, University Of California, Yu-Chin Hsu
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ISBN
9780792395973
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