Sets out not only to teach VHDL but also to describe how to use VHDL when designing an electronic system with modern design tools. The synthesis tools Synopsys,... » 

Sets out not only to teach VHDL but also to describe how to use VHDL when designing an electronic system with modern design tools. The synthesis tools Synopsys, Mentor Graphics and ViewLogic are used. It describes an academic approach, and also explains how VHDL is used in real industrial projects. «