Book
Design And Modeling Of Pll Based Cdr For Inter Chip Communications
Design and Verilog-A Modeling of Phase-Locked Loop Based Clock and Data Recovery Integrated Circuit for 10 Gb/s Intra/Inter Chip Communications in SoC «
Score:
Reviews:
Times tipped:
Times read:
Author(s):
Category:
ISBN
9783639185546
Welcome to Boeklezers.nl
Boeklezers.nl is a network for social reading. We help readers discover new books and authors, and bring readers in contact with each other and with writers. Read more ».
Reviews of Design And Modeling Of Pll Based Cdr For Inter Chip Communications by Maher Assaad
There are no reviews for this book yet.
Idea box
